Sravanth Chebrolu, Srinivas Boppu and Linga Reddy Cenkeramaddi, “Hardware Acceleration of a CNN-based Automatic Modulation Classifier,” has been accepted for publication in the 2023 Southern Conference on Programmable Logic- SPL2023.
Abstract: Automatic modulation classification (AMC) has found its place in numerous applications, ranging from cognitive radio and adaptive communication to electronic reconnaissance and spectrum interference detection. Several attempts have been made to develop a high-accuracy modulation classifier using machine learning based convolutional neural networks (CNNs). This paper considers one such model, which uses a fixed boundary range empirical wavelet transform and deep CNN, and accelerates the model on the ZCU104 FPGA board to achieve fast classification times. The proposed accelerator can achieve a maximum classification accuracy of 96% for +8 dB signal-to-noise ratio (SNR) radio signals. Compared to similar works, the accelerator performs reasonably well for low SNR ratios (≤ +6 dB). Furthermore, the model is implemented on an edge CPU device (Raspberry Pi), and our accelerator is 50× faster than the CPU implementation. Our design achieves a reasonable throughput of 1.8K classifications/sec and a classification time of 550 µs per sample.
Keywords: Modulation Classification, Hardware Acceleration, Deep Learning, Convolutional Neural Networks, Vitis AI
PUDI DHILLESWARARAO, SRINIVAS BOPPU, M. SABARIMALAI MANIKANDAN, LINGA REDDY CENKERAMADDI, “Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey” has been accepted for publication in IEEE Access (2022).
Keywords: Field programmable gate arrays, Computer architecture, Deep learning, AI accelerators, Hardware acceleration, Graphics processing units, Feature extraction.
Abstract: In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.
More details: DOI: 10.1109/ACCESS.2022.3229767